Cadence Q DRIVE SERIES Uživatelský manuál stáhnout pdf (Strana 3)

(ii) Prepare the “environment” template for Synthesis, “setup.tcl”

Generate the setup.tcl file in “synthesis” directory.

setup.tcl file:

proc setup {} {

# show all commands on the monitor as they are executed

set_global echo_commands true

# set maximum fanout limit at each synthesized gate

set_global fanout_load_limit 12

# read all the library cells used during synthesis

read_alf /apps/cadence//jointfilesconvert/375363/bg40/lib/lca500k.alf

# transform lca500kv to a name called "target_techology" for future use

set_global target_technology lca500kv

# include wireload models into library elements

read_library_update /apps/cadence//jointfilesconvert/375363/bg40/lib/lca500k.wireload3

}

(iii) Synthesizing the Verilog RTL code

(a) Launch ac_shell:

To launch synthesis, type ac_shell -gui at the prompt sign when you are still in

“synthesis” directory.

An “ac_shell” window will pop up.

(b) Reading setup.tcl file:

Go to the prompt sign on the “ac_shell” window.

To have Synthesis tool read your setup.tcl file type:

ac_shell> source setup.tcl.

To run the script in the setup.tcl file type:

ac_shell> setup

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Cadence Q DRIVE SERIES Uživatelský manuál Strana 3